In the manufacture of semiconductor products such as integrated circuits, individual electrical devices are formed on or in a semiconductor substrate, and are thereafter interconnected to form electrical circuits. Interconnection of these devices within an integrated circuit, also referred to as metallization, is typically accomplished by forming a multi-level interconnect network structure in layers formed over the electrical devices, by which the device active elements are connected to other devices to create the desired circuits. Conductive materials such as aluminum, aluminum-silicon alloys, copper, and the like, are employed to provide relatively low resistance connections between components and devices.
In one example of metallization, individual wiring layers within a multi-level network can be formed by depositing an insulating or dielectric layer over the discrete devices or over a previous interconnect layer, and patterning and etching contact openings such as vias. Conductive material, such as tungsten is then deposited into the vias to form inter-layer contacts. A conductive layer may then be formed over the dielectric layer and patterned to form wiring interconnections between the device vias, thereby creating a first level of basic circuitry. Dielectric material is then deposited over the patterned conductive layer, and the process may be repeated any number of times using additional wiring levels laid out over additional dielectric layers with conductive vias therebetween to form the multi-level interconnect network. This type of metallization is adequate for some conductive materials, such as aluminum. However, other conductive materials are not well suited to being patterned and thus, are not typically employed in the above metallization process.
Copper is a particularly desirable material for metallization because of its low resistivity (about 1.7 micro ohm-cm) and superior resistance to electromigration compared with aluminum and/or aluminum alloys. However, etching and patterning of copper is problematic. Copper patterning difficulties have been avoided or mitigated through the use of single and dual damascene interconnect processes in which cavities are formed (etched) in a dielectric layer. Damascene processing involves the creation of interconnect lines by first etching a trench or canal in a planar dielectric layer and then filling that trench with metal, such as aluminum or copper. In dual damascene processing, a second level is involved where a series of holes (contacts or vias) are etched and filled in addition to the trench. Thus, copper is deposited into the trenches and/or vias and over the insulative layer, followed by planarization using, e.g., a chemical mechanical polishing (CMP) process to leave a copper wiring pattern including the desired interconnect metal lines inlaid within the dielectric layer trenches and vias. In the single damascene process copper trench patterns or vias are created which connect to existing interconnect structures thereunder, whereas in a dual damascene process, both vias and the trenches are filled at the same time using a single copper deposition and a single CMP planarization. The advantage of damascene processing is that it eliminates the need for metal etch, which is advantageous for copper interconnects.
Conventional single and dual damascene interconnect processing typically includes the formation of via cavities through a dielectric layer, in which the via etch process stops on an etch-stop layer underlying the dielectric. In the single damascene case, an etch-stop layer etch process is then performed to expose the underlying structure, such as a conductive feature (e.g., silicide contact or copper feature) in a pre-existing interconnect layer. The via cavity is then filled with copper, an anneal is performed, and the wafer is planarized, after which further interconnect levels may then be fabricated. In the dual damascene case, a trench cavity is etched and an etch-stop layer etch is performed to expose the underlying structure. The via and trench cavities are simultaneously filled with copper, annealed, and the wafer is planarized thereby forming the copper interconnects and contacts.